This invention relates to the manufacture of semiconductor devices, and more particularly to a method for manufacturing insulated gate field effect transistor devices having extremely shallow source and drain regions and reduced overlap capacitances between the gate and the source and drain regions.
In the manufacture of insulated-gate field-effect transistor (hereinafter referred to as IGFET) devices, such as integrated circuits, it is generally desirable to reduce the conduction channel lengths of the IGFETs for the purpose of increasing the packing density and operating speed of the device. It is also generally desirable, from the standpoint of increasing device speed, to reduce the gate to source and drain overlap capacitances of the IGFETs and to provide the device with lower resistance interconnections. Recent advances in lithographic and etching techniques have made it possible to form IGFETs having channel lengths of less than 1 .mu.m. However, in order to avoid undesirable short channel effects, such as threshold voltage falloff, in such submicron channel length IGFETs, the source and drain regions of the IGFETs must be made extremely shallow. For example, in a silicon N-channel metal-oxide-semiconductor (MOS) transistor having an effective channel length of 0.5 .mu.m, a gate oxide thickness of 250 Angstroms and a net channel doping concentration of 4.times.10.sup.16 cm.sup.-3, short channel effects are substantially avoided if the depths of the source and drain regions extend less than 1000 Angstroms below the surface of the channel. Furthermore, the sheet resistance of the source and drain regions of such a transistor must be relatively low (e.g., less than 70 ohms per square) so as not to reduce the current conduction capability of the transistor. Therefore, the fabrication of submicron channel length IGFETs requires the formation of source and drain regions which are extremely shallow and which have low sheet resistances.
In the prior art, source and drain regions of IGFETs are most frequently formed by either conventional diffusion or by ion implantations. In the case of conventional diffusion the source and drain regions are formed by diffusing an appropriate dopant impurity into selected areas of a semiconductor surface from an appropriate gas dopant source or from a predeposition source such as a doped semiconductor oxide layer or a doped polycrystalline semiconductor layer in contact with the surface. The impurity is then thermally driven to a desired depth below the surface. However, because the rate of transport of the dopant impurity into the surface by conventional diffusion is generally limited by the solid solubility of the impurity at the diffusion temperature, conventional diffusion followed later by a standard annealing step has the disadvantage of ordinarily not being able to provide an extremely shallow diffused region with a sufficiently high impurity level to provide the region with a low sheet resistance.
In the case of ion implantation, the source and drain regions are formed by bombarding selected areas of the semiconductor surface with an energetic beam of an appropriate ionized dopant impurity. Although ion implantation can provide extremely shallow impurity regions having very high impurity levels, such regions tend to have high sheet resistances owing to lattice damage in the implanted region caused by the ion implantation. Such lattice damage ordinarily results in a significant portion of the dopant impurity not being in proper substitutional lattice sites and a lowering of the carrier mobility in the implanted region. Consequently, ion implantation has the disadvantage in that a post-implantation annealing treatment for repairing the lattice damage is ordinarily required to lower the sheet resistance of an implanted region. Such an annealing treatment tends to cause the region to diffuse to an excessive depth. For that reason, ion implantation cannot ordinarily be used to provide low sheet rsistance source and drain regions of less than 2000 Angstroms in depth. Therefore, a need exists for a method for manufacturing IGFET devices which provides transistors having extremely shallow source and drain regions of low sheet resistance.
Presently, MOS transistors are preferably fabricated by a self-aligned gate technology in which a patterned gate electrode serves as a diffusion or implantation mask for the formation of the source and drain regions. In such transistors, the gate to source and drain overlap capacitances arise primarily from the lateral diffusion of the source and drain regions under the gate electrode. Since the extent of lateral diffusion of the source or drain region is proportional to the depth of such a region, using shallower source and drain regions generally contributes to reducing the overlap capacitances.
However, even in a self-aligned gate MOS technology, it is generally desirable to achieve further reductions in the overlap capacitances. Such reductions are preferably achieved by providing appropriate offsets between the edges of the gate electrode and the masks for the source and drain regions.
A prior art technique for providing such offsets is to reduce the width of the gate electrode by oxidation after the formation of the source and drain regions. However, this technique has the disadvantage in that the thermal treatment required for oxidizing the gate electrode drives the source and drain regions to excessive depths.
Moreover, it is known that the gate electrode can be oxidized before the implant. But in that case, as well as in the case where oxidation occurs after the formation of the source and drain regions, the length of the gate will be reduced, and the channel length will be variable. Also, in either case the surfaces of the source and drain regions are unavoidably displaced below the surface of the channel.
Another prior art technique for providing the above-described offset is to over-etch the gate electrode during patterning to form an overhanging photoresist layer above the gate electrode. The overhanging photoresist layer is then used, directly or indirectly, to mask the formation of the source and drain regions. However, this technique has the disadvantage in that the extent of the over-etching of the gate electrode is difficult to control, and the gate electrode acquires undesirable nonvertical sidewalls. Therefore, a need also exists for a method for manufacturing an IGFET which provides an offset between the gate electrode and the mask for forming the source and drain regions but which does not require oxidation or over-etching of the gate electrode.
In a typical self-aligned gate MOS technology, the gate electrodes of the transistor are provided by a layer of polycrystalline silicon (polysilicon). The polysilicon layer also provides a first level of interconnection for the transistors and other components of the device. A second level of interconnection is typically provided by a layer of an appropriate metal. Since the sheet resistance of even a heavily doped polysilicon layer is typically several orders of magnitude greater than that of the metal layer, it is desirable, for the purpose of increasing device speed, to reduce the sheet resistance of the polysilicon layer. A known technique for reducing the sheet resistance of the polysilicon layer is to form a layer of an appropriate metal silicide, such as tantalum silicide, on a surface of the polysilicon layer. In the prior art, the silicide layer is formed over the entire polysilicon layer prior to patterning. However, in some instances metal silicide layers are also required as contact layers for the source and drain regions. In those instances, it is desirable from the standpoint of reducing manufacturing cost to form the silicide layers for the polysilicon layer and the source and drain regions in the same processing step. Therefore, a need exists for a method for manufacturing an IGFET device which forms those silicide layers in a single processing step.
In some cases of practical importance, a need also exists for a relatively thin silicide layer for the source and drain regions (thereby establishing a prescribed low resistivity while maintaining shallow junctions) which layer is compatible with a relatively thick silicide layer (even lower resistivity) patterned to form part of the gate electrode.